TSMC's N2 process node — colloquially called "2nm" — is entering volume production in 2026. For the companies designing AI chips, it represents the first transition to gate-all-around (GAA) transistor architecture in TSMC's roadmap, a technically significant shift after more than a decade of FinFET dominance.
Understanding what N2 actually delivers requires separating TSMC's published performance claims from the speculation that surrounds each new node announcement.
The GAA Transition: Why It Matters
FinFET transistors — dominant since TSMC's 16nm node — use a fin-shaped silicon channel with the gate wrapping around three sides. As dimensions have shrunk toward physical limits, FinFET's ability to control leakage current has become increasingly constrained. Gate-all-around (GAA) nanosheet transistors wrap the gate fully around the channel on all four sides, improving electrostatic control and reducing leakage at smaller dimensions.
According to TSMC's publicly disclosed N2 node documentation, N2 delivers approximately 10-15% speed improvement at the same power, or roughly 25-30% power reduction at the same speed, compared to N3E — TSMC's previous leading-edge node. These are the performance targets TSMC has communicated; actual product-level gains depend on design implementation.
- First TSMC node to use GAA nanosheet transistors — fundamental architecture change
- ~10-15% speed improvement or ~25-30% power reduction vs N3E at equivalent settings
- Apple confirmed as lead customer; A20 chip (iPhone 18) expected on N2
- Volume production targeted for second half of 2026
- Samsung and Intel both developing competing 2nm-class nodes with different architectures
Who Gets the First Wafers
Apple has historically been TSMC's lead customer for new process nodes, securing priority allocation in exchange for guaranteed volume. Apple's A20 chip, expected in the iPhone 18, is widely reported to be among the first high-volume N2 products — consistent with Apple's multi-year pattern of leading TSMC node transitions.
NVIDIA's next-generation AI GPU architecture (the successor to Blackwell) is expected to target N2 for the compute dies, though the exact product configuration — whether fully on N2 or using a split between N2 and N3P for different components — has not been officially confirmed as of early 2026.
Supply Constraints Are Real
Every TSMC node transition follows a consistent pattern: slow yield ramp in the first six to nine months as process engineers identify and address defect sources, then rapid improvement toward volume production. N2's GAA transition is architecturally more complex than the N3 transition, which analysts widely expect will make the initial yield ramp slower than N3's.
For companies planning AI chip programs around N2, this has practical consequences: wafer allocation in the first year of production will be constrained, and lead customers with long-term volume commitments will receive priority. Companies without existing TSMC relationships or volume commitments face meaningful risk of delayed access.
The Competitive Landscape
Samsung's 2nm-class GAA process (SF2) has faced yield challenges that caused several potential customers to redirect orders to TSMC. Intel's 18A process — which uses Intel's own GAA architecture called RibbonFET — is targeting a similar timeframe and has secured a small number of external customers. Neither challenger has demonstrated the manufacturing maturity to threaten TSMC's position at the leading edge in the near term, though both represent genuine long-term competitive efforts.
For the AI industry specifically, TSMC's N2 node matters because it will define the performance envelope of AI training and inference chips through 2027 and 2028. The companies that secure allocation early will have a meaningful infrastructure advantage during that window.